4 am

Its 4am and my eyes refuse to go to sleep.

Just now I was thinking about the exam week that has finally passed.

Finally.

It is soo much harder this time. Harder than undergrad, when life was carefree and simple. Harder when i have a book on one hand and a toddler tugging on another, pleading for attention. Soo much harder when dear husband had to go outstation on thursday to monday while i have a paper and presentation on thursday, another presentation on friday, another paper on monday, and dear toddler to attend to. Its so much harder well beyond the complexity of the exam questions and too much assignments.

Harder but not un-DO-able.

Although the season has left, the aftertaste still lingers. I am all exhausted. I need a break. Just for a while.

I'm writing this down so I'll remember this moment. Just for the sake of memory.

Makan USB Minum USB Tido USB

Everything USB!

Its the first thing that pop-up into my mind when i wake-up and the last thing that leave my mind every night when i force my self to sleep. I know i have no life when i speend my weekend in front of my lappy recompiling the verilog program over and over and over and over again. Everytime i fix one error, another error is generated! And dont get me started on the simulation.

Up to this point i've only succeeded the speed handshaking process. U know USB in general have 3 speeds; low speed, full speed (usb1.1), and high speed (usb2.0).. Yeah so my controller now can identify and switch to the according mode. Thats it. Hehe.. And it took me almost 3 days but its worth it when i finally manage to simulate the conditions today. At least now i hv some results to present during the presentation. Even its soo micromini...

I only hv 3 more days before THE DAY (think band of brothers). Work hard and no sleep is the answer.

Saira, i know exactly how u feel when u said u hate Einstein for discovering E=mc2. Life is much easier when people thought the earth is flat.


Oh well.. Back to my dungeon. And yeah.. USB..

How Much Are You Willing To Spend..

While browsing the library opac system searching for reference materials, I came across this one book that was published in 1974. Thinking that maybe I can purchase a latest edition from Amazon(dot)Com, I'm shocked to find that few people were actually selling the 1974 editions. 5 people if i'm not mistaken, but thats not the thing that jolt me out of my sleepy mind. The cheapest one is listed at 0.85k USD! Notice the 'k' and 'USD'.. a rough convert to RM3k..

The one I borrowed from the library is pretty battered n old looking.. I have no intention to sell this anyway, hehe..

I find myself engrossed in these books, no kidding!

My favourite reading to date.. I wish I can write something like this when I'm old and retired..

A little excerpt about the moment Wilkinson ADC was invented:

"The germ of the solution came to me as, leaving Chalk River, I sailed back to England from New York in April 1 946 on the Queen Elizabeth's first trip after reconversion from a troop ship. The idea was that you could, very stably, convert a pulse amplitude into a time in various ways, for example, as I eventually did it, by catching the pulse at its peak and giving it a linear run-down. You could then, again very stably, measure this time by using it to gate an oscillator in the process now known as analogue-to-digital conversion. The idea is so blazingly obvious that it has never ceased to amaze me how long it took to find."

A point to ponder:

"With ADC-based multichannel analyzers in the thousands all over the world,
I am often told that it must be nice to be rich. So it may well be, but I do not
know: I did not patent the device, and I never made a penny."



Last but not least, my little hero..

Da!

Verilogger

Verilog or VHDL? thats the question.. i believe dats the question most ppl ask at the initial stage of their research. mestila concentrate satu je kan, supaya tak serabut kepala?

akan tetapi aku yg bijak yg dari awal planning to use VHDL (since itu yg aku tau 'sikit-sikit') telah menceburkan diri ke verilog class. For sure la semua assignment dlm verilog.. n pakai altera instead of xilinx.. tahniah! sebab berjaya menkopiuskan otak sendiri..

my final assignment for this subject : design on-chip usb controller (Purp! nantikan panggilan telefon ku! hehe).. padahal research nnt nk buat ethernet controller..

ish ish ishhhh...

for the sake of knowledge.. hope i wont forget it by the time i'm back to work (dats is in 1.5 years time ;) )...


Maaf skill blogging yg makin depleting:
1. takde masa
2. kalau ada masa pun rasa bersalah sbb mcm patut guna masa tu utk siapkan assignment, so xyah angkut buku n board berat2 n balik boleh main2 dengan papa n awisy macam dulu2 tanpa rasa bersalah.. mcm yg tgh dirasai sekarang...

Untuk menceriakan hati, telah mendisplay tarikh birthday pada 7-segments itu

wayar-wayar yang menyerabutkan meja tapi bukan perasaan..

akhir sekali.. meja orang rajin!

module NakBalikKejapLagiOi (icelemon_tea, laptop, traffic_jam);
endmodule

The Ramblings of Mine

Finally, i think my supervisor is satistifed w my proposal and i can take a breather (ada hati). During our lab progress report presentation, my heart ws thumping as i'm afraid that he would shut down my idea (again). When i heard a faint "ok good" remark at the end of the presentation, my heart ballooned. (ni baru part proposal!). Finally! I cn start my work without wondering which part is gonna be my "novel" research - the new contribution to the body of knowledge. Makantaklalutidotaklelapmanditak basah bila terfikir ok. Nasib baik baru master. And i think being in engineering line i.e. electronics make it soo much harder. We are used to providing technical solution. Not inventing the fundamental of the solution itself. To me, dats more of physicist job. Heheh. Tapi for the mean time aku boleh menarik nafas lege. Plus i think Insyallah i can achieve my research objectives hence solving the problem stated... Hehehe.. Aminnnnn.

Refreshing mental list:
1. Research progress report n presentation - checked
2. Research methodology assignment - done n hope i cn present it to the class next week.
3. AV process - 2 assignments that need a kickstart a.s.a.p coz the due is very near
4. Verilog big assigment i.e. Final - also need a kick start. Gonna hv group discussion today. N got replacement class this afternoon.


Caiyok!

Papadom Sangat BEST!

Watched after my test today. HIGHLY recommended :D

Biar Benar?

Kehidupan yang hectic:

1 presentation today
1 presentation tomorrow
1 test the next day

On top of that 2 assignments and 1 really big assignments to be completed by exam weeks. Semua belum start apa. YIKES!

I'm a slave to my own decision but not regrets.