Wednesday, October 14, 2009

Verilogger

Verilog or VHDL? thats the question.. i believe dats the question most ppl ask at the initial stage of their research. mestila concentrate satu je kan, supaya tak serabut kepala?

akan tetapi aku yg bijak yg dari awal planning to use VHDL (since itu yg aku tau 'sikit-sikit') telah menceburkan diri ke verilog class. For sure la semua assignment dlm verilog.. n pakai altera instead of xilinx.. tahniah! sebab berjaya menkopiuskan otak sendiri..

my final assignment for this subject : design on-chip usb controller (Purp! nantikan panggilan telefon ku! hehe).. padahal research nnt nk buat ethernet controller..

ish ish ishhhh...

for the sake of knowledge.. hope i wont forget it by the time i'm back to work (dats is in 1.5 years time ;) )...


Maaf skill blogging yg makin depleting:
1. takde masa
2. kalau ada masa pun rasa bersalah sbb mcm patut guna masa tu utk siapkan assignment, so xyah angkut buku n board berat2 n balik boleh main2 dengan papa n awisy macam dulu2 tanpa rasa bersalah.. mcm yg tgh dirasai sekarang...


Untuk menceriakan hati, telah mendisplay tarikh birthday pada 7-segments itu


wayar-wayar yang menyerabutkan meja tapi bukan perasaan..


akhir sekali.. meja orang rajin!





module NakBalikKejapLagiOi (icelemon_tea, laptop, traffic_jam);
endmodule

2 comments:

Mas said...

I also feel the same mimi.. when i go back to work.. will i remember everything i learned? macam idak jer.. My memories is like a chipsmore...

Right now, I try to enjoy living here instead of studying here..

PurPle said...

hahaaa... mas, aku ni lg ingatan volatile. movie yg tgk kt wyng pun bleh lupa jln citer.

mimi, gd luck in ur assignment. really hope u can execute it. sorry couldnt help much. i remember the time aku susah hati pasal kene buat benda ni especially thinking about the PC side. so, of course, if u manage, aku nak gak the result ;-). btw, kite geng verilog... heheee.